Töökindlate Arvutisüsteemide Uurimise Keskus

Digitaalsüsteemide disain ja testimine

Kompetents:

digitaalsüsteemide disain ja testimine, isetestivad süsteemid, tõrkekindlus

Uurimisrühma põhikoosseis:

Raimund Ubar, TTÜ arvutitehn. inst. prof. (uurimisrühma juht)
-- tel. 620 2252, epost raiub (at) pld . ttu . ee
Marina Brik, TTÜ arvutitehn. inst. teadur
Peeter Ellervee, TTÜ arvutitehn. inst. dots. (kuni aug. 2004), prof. (al. sept. 2004)
Eero Ivask, TTÜ arvutitehn. inst. teadur
Gert Jervan, TTÜ arvutitehn. inst. erak. vanemteadur (al. juuni 2005)
Artur Jutman, TTÜ arvutitehn. inst. teadur (kuni 2005), vanemteadur (al. 2005)
Margus Kruus, TTÜ arvutitehn. inst. dir., dots.
Elmet Orasson, TTÜ arvutitehn. inst. teadur
Jaan Raik, TTÜ arvutitehn. inst. van.-tead.
Aleksandr Sudnitsõn, TTÜ arvutitehn. inst. dots.
Kalle Tammemäe, IT Kolledži rektor / TTÜ arvutitehn. inst. dots. (kuni 2005), erak. professor (al. 2005)

Doktorandid:

Margit Aarna, TTÜ doktorant (al. sügis 2003)
Anton Arhipov, TTÜ doktorant (al. sügis 2005)
~~Marina Brik, TTÜ doktorant (sügis 1994-sügis 2002, kaitsnud)~~
Sergei Devadze, TTÜ doktorant (al. sügis 2004)
~~Jelena Fomina, TTÜ doktorant (sügis 1999-sügis 2005, kaitsnud)~~
Vineeth Govind, TTÜ doktorant (al. sügis 2005)
Hanno Hantsson, TTÜ doktorant (al. sügis 2006)
~~Eero Ivask, TTÜ doktorant (sügis 1998-kevad 2006, kaitsnud)~~
Maksim Jenihhin, TTÜ doktorant (al. sügis 2004)
~~Artur Jutman, TTÜ doktorant (sügis 1999-sügis 2004, kaitsnud)~~
Sergei Kostin, TTÜ doktorant (al. sügis 2007)
Anna Krivenko, TTÜ doktorant (al. sügis 2005)
Helena Kruus, TTÜ doktorant (al. sügis 2003)
Dmitri Mihhailov, TTÜ doktorant (al. sügis 2007)
~~Elmet Orasson, TTÜ doktorant (sügis 2003-sügis 2007, kaitsnud)~~
Uljana Reinsalu (Boiko), TTÜ doktorant (al. sügis 2005)
Tatjana Shchenova, TTÜ doktorant (al. sügis 2005)
Mihkel Tagel, TTÜ doktorant (al. sügis 2006)
Anton Tšertov , TTÜ doktorant(al. sügis 2007)
Taavi Viilukas, TTÜ doktorant (al. sügis 2006)

Publikatsioone 2003:

S. Devadze, E. Fomina, M. Kruus, and A. Sudnitson. Web-based system for sequential machines decomposition. In Proc. of IEEE Region 8 Int. Conf. Computer as a Tool, EUROCON 2003 (Ljubljana, Sept. 2003), v. 1, pp. 57-61. 2003. article at IEEExplore
S. Devadze, R. Gorjachev, A. Jutman, E. Orasson, V. Rosin, R. Ubar. E-learning tools for digital test. In Distance Learning - Educational Environment of the XXI Century, pp. 336-342. Minsk, 2003.
P. Ellervee, J. Raik, V. Tihomirov. Fault emulation on FPGA: a feasibility study. In Proc. of 21st IEEE NORCHIP Conf., 2003 (Riga, Nov. 2003), pp. 92-95. 2003.
E. Fomina, A. Keevallik, M. Kruus, A. Sudnitson. A decomposition procedure for register-transfer level power management. In Proc. of Int. Conf. on Computer Systems and Technologies, CompSysTech 2003 (Sofia, June 2003), v. 1, pp. 21-26. 2003.
E. Fomina, A. Sudnitson. Synthesis of finite state machines networks guided by information relationships. In Proc. of Int. Conf. on the Experience of Designing and Application of CAD Systems in Microelectronics, CADSM 2003 (Slavske, Feb. 2003). 2003.
E. Gramatova, M. Hristov, W. Kuzmicz, V. Lantsov, M. Lobur, V. Nelayev, V. Stepanets, R. Ubar, H.-D. Wuttke. Results of international cooperation for development and exchange of Web-based educational materials. In Distance Learning - Educational Environment of the XXI Century, pp. 17-23. Minsk, 2003.
V. Hahanov, R. Ubar. First East-West Design and Test Conference. IEEE Design & Test of Computers, v. 20, n. 6, p. 103, 2003.
V. Hahanov, R. Ubar, S. Hyduke. Back-traced deductive-parallel fault simulation for digital systems. In Proc. of Euromicro Symp. on Digital System Design, DSD 2003 (Belek-Antalaya, Sept. 2003), pp. 370-377. IEEE, 2003. doi: 10.1109/dsd.2003.1231969
G. Jervan, P. Eles, Z. Peng, R. Ubar, M. Jenihhin. Hybrid BIST time minimization for core-based systems with STUMPS architecture. In Proc. of 18th Int. Symp. on Defect and Fault Tolerance in VLSI Systems, DFT 2003 (Boston, MA, Nov. 2003), pp. 225-232. IEEE, 2003. article at IEEExplore
G. Jervan, P. Eles, Z. Peng, R. Ubar, M. Jenihhin. Test time minimization for hybrid BIST of core-based systems. In Proc. of 12th Asian Test Symp., ATS 2003 (Xi'an, Nov. 2003), pp. 318-323. IEEE, 2003. doi: 10.1109/ats.2003.1250830
A. Jutman. On SSBDD model size and complexity. In Proc. of 4th Electronic Circuits and Systems Conf. (Bratislava, Sept. 2003), pp. 17-22. 2003.
A. Jutman, A. Sudnitson, R. Ubar, Digital design learning system based on Java applets. In Proc. of 4th Ann. Conf. of LTSN Subject Centre for Information and Computer Sciences (Galway, Aug. 2003), pp. 183-187. 2003.
A. Jutman, A. Sudnitsõn, R. Ubar. Web-based applet for teaching boundary scan standard IEEE 1149.1. In Proc. of 10th Int. conf. on Mixed Design of Integrated Circuits and Systems, MIXDES 2003 (Lodz, June 2003), pp. 584-589. 2003.
A. Jutman, A. Sudnitson, R. Ubar. Web-based training system for teaching principles of boundary scan technique. In Proc. of 14th EAEEIE Ann. Conf. on Education in Electrical and Information Engineering, EAEEIE 2003 (Gdansk, June 2003), 4 pp. 2003.
A. Jutman, A. Sudnitsõn, R. Ubar, D. Wuttke. Java applets support for an asynchronous-mode learning of digital design and test. In Proc. of 4th Int. Conf. on Information Technology Based Higher Education and Training, ITHET 2003 (Marrakech, July 2003), pp. 397-401. IEEE, 2003.
M. Kruus, A. Sudnitson. Virtual European Department of Computing project: problems and perspectives. In Proc. of 30th Int. Conf. on Information Technologies in Science, Education, Telecommunication, Business, IT+SE 2003 (Yalta-Gurzuf, May 2003), pp. 280-283. 2003.
A. Mekler, J. Raik. Multiple-objective backtrace for solving test generation constraints. In Proc. of Int. Symp. on System-on-Chip, (Tampere, Nov. 2003), pp. 123-126. IEEE, 2003. doi: 10.1109/issoc.2003.1267732
J. Raik, T. Nõmmeots, R. Ubar. New method of testability calculation to guide RT-level test generation. In Proc. of 4th IEEE Latin-American Test Workshop, LATW 2003 (Natal, Feb. 2003), pp. 46-51. 2003.
J. Raik, R. Raidma, R. Ubar. Explorations in low area overhead DfT techniques for sequential BIST. In Proc. of 21st IEEE Conf. NORCHIP 2003 (Riga, Nov. 2003), pp. 220-223. 2003.
A. Schneider, K.-H. Diener, G. Elst, R. Ubar, E. Ivask, J. Raik. Integration of digital test tools to the Internet-based environment MOSCITO. In Proc. of 7th World Multiconf. on Systemics, Cybernetics and Informatics, SCI 2003 (Orlando, July 2003), pp. 136-141. IIIS, 2003.
A. Sudnitson, A. Jamshanov. A FSM decomposition method for mixed synchronous / asynchronous implementation. In Proc. of 17th Int. Conf. on Systems for Automation of Engineering and Research, SAER 2003 (Varna, Sept. 2003). 2003.
R. Ubar. Decision diagrams and digital test. In Proc. of 6th Int. Wksh. on Electronics, Control, Measurement and Signals (Liberec, June 2003), pp. 266-273. 2003.
R. Ubar. Design error diagnosis with re-synthesis in combinational circuits. J. of Electronic Testing: Theory and Applications, v. 19, n. 1, pp. 73-82. 2003. doi: 10.1023/a:1021948013402
R. Ubar. E-learning tools for the field of electronics design and test. In Proc. of 4th Int. Conf. on Information Technology Based Higher Education and Training, ITHET 2003 (Marrakech, July 2003), pp. 285-290. 2003.
R. Ubar. Mapping faults in hierarchical testing of digital systems. In Proc. of Int. Conf. on Computer, Communication and Control Technologies, CCCT '03 (Orlando, July/Aug. 2003), pp. 14-19. IIIS, 2003.
R. Ubar. Mapping physical defects to logic level for defect oriented testing. In Proc. of Int. Symp. on Signals, Circuits and Systems, SCS 2003 (Iasi, July 2003), v. 2, pp. 453-456. IEEE, 2003. article at IEEExplore
R. Ubar, M. Jenihhin, G. Jervan, Z. Peng. Test time minimization for hybrid BIST with test pattern broadcasting. In Proc. of 21st IEEE NORCHIP Conf., 2003 (Riga, Nov. 2003), pp. 112-116. 2003.
R. Ubar, E. Orasson. E-learning tool and exercises for teaching digital test. In Proc. of 2nd IEEE Conf. on Signals, Systems, Decision and Information Technology (Sousse, March 2003), CIT-6, pp. 1-6. 2003.
R. Ubar, J. Raik. Testing strategies for networks on chip. In A. Jantsch, H. Tenhunen, eds., Networks on Chip, pp. 131-152. Kluwer Acad. Publ., 2003. doi: 10.1007/0-306-48727-6_7
R. Ubar, J. Raik, B. Klüver. Algorithms for hierarchical fault simulation in digital systems. In Proc. of 10th Int. Conf. on Mixed Design of Integrated Circuits and Systems, MIXDES 2003 (Lodz, June 2003), pp. 530-535. 2003.

Publikatsioone 2004:

M. Brik, E. Ivask, J. Raik, R. Ubar. On using genetic algorithm for test generation. In Proc. of 9th Biennial Baltic Electronics Conf., BEC 2004 (Tallinn, Oct. 2004), pp. 233-236. Tallinn Univ. of Techn., 2004.
M. Brik, J.Raik, R. Ubar, E. Ivask. GA-based test generation for sequential circuits. In Proc. of 2nd East-West Design and Test Wksh., EWDTW 2004 (Alushta, Sept. 2004), pp. 30-24. 2004
E. Dubrova, P. Ellervee, D. M. Miller, J. C. Muzio, A. J. Sullivan. TOP: an algorithm for three-level combinational logic optimisation. IEE Proc.: Circuits, Devices and Systems, v. 151, n. 4, pp. 307-314, 2004. doi: 10.1049/ip-cds:20040159
P. Ellervee, J. Raik, V. Tihhomirov. Environment for fault simulation acceleration on FPGA. In Proc. of 9th Biennial Baltic Electronics Conf., BEC 2004 (Tallinn, Oct. 2004), pp. 217-220. Tallinn Univ. of Techn., 2004.
P. Ellervee, J. Raik, V. Tihhomirov, K. Tammemäe. Evaluating fault emulation on FPGA. In J. Becker, M. Platzner, S. Vernalde, eds., Proc. of 14th Int. Conf. on Field Programmable Logic and Application, FPL 2004 (Leuven, Aug./Sept. 2004), v. 3203 of Lect. Notes in Comput. Sci., pp. 354-363. Springer, 2004. article at SpringerLink
P. Ellervee, J. Raik, V. Tihhomirov, R. Ubar. FPGA based fault emulation of synchronous sequential circuits. In Proc. of 22nd IEEE NORCHIP Conf., 2004 (Oslo, Nov. 2004), pp. 59-62. 2004. doi: 10.1109/norchp.2004.1423822
E. Fomina, A. Sudnitson. Information relationships for decomposition of finite state machine. In Proc. of 2nd IEEE East-West Design and Test Wksh., EWDTW 2004 (Alushta, Sept. 2004), pp. 41-47. 2004.
E. Fomina, A. Sudnitson, R. Vasilyev. FSM's network encoding guided by information relationship measure. In Proc. of 6th Int. Wksh. on Boolean Problems (Freiberg, Sept. 2004), pp. 55-62. 2004.
E. Fomina, A. Sudnitsyn, R. Vasilyev. Optimization of FSMs network by new encoding strategy. In Proc. of 9th Biennial Baltic Electronics Conf., BEC 2004 (Tallinn, Oct. 2004), pp. 119-122. Tallinn Univ. of Techn., 2004.
E. Fomina, P. Ellervee, M. Kruus, A. Sudnitson, K. Tammemae. Digital synthesis tools for education and research. In Proc. of 18th Int. Conf. on Systems for Automation of Engineering and Research, SAER 2004 (Varna, Sept. 2004), pp. 160-164. 2004.
V. Hahanov, R. Ubar. 2nd IEEE East-West Design and Test Workshop. IEEE Design & Test of Computers, v. 21, n. 6, pp. 594, 2004. doi: 10.1109/mdt.2004.82
E. Ivask, P. Ellervee. VHDL front-end for high-level synthesis tool xTractor. In Proc. of 9th Biennial Baltic Electronics Conf., BEC 2004 (Tallinn, Oct. 2004), pp. 111-114. Tallinn Univ. of Techn., 2004.
E. Ivask, J. Raik, R. Ubar, A. Schneider. Web-based environment: remote use of digital electronics test tools. In L. M. Camarinha-Matos, ed., Virtual Enterprises and Collaborative Networks, v. 149 of Int. Feder. of Inform. Processing, pp. 435-442. Kluwer Acad. Publ., 2004. doi: 10.1007/1-4020-8139-1_46
E. Ivask, A. Jutman, E. Orasson, J. Raik, R. Ubar, H.-D. Wuttke. Research Environment for Teaching Digital Test. In Proc. of Int. Conf. IWK (Ilmenau, Sept. 2004), pp. 468-473. 2004.
G. Jervan, Z. Peng, R. Ubar, O. Korelina. An improved estimation methodology for hybrid BIST cost calculation. In Proc. of 22nd IEEE NORCHIP Conf., 2004 (Oslo, Nov. 2004), pp. 297-300. 2004. doi: 10.1109/norchp.2004.1423882
A. Jutman. At-speed on-chip diagnosis of board-level interconnect faults. In Proc. of 9th IEEE European Test Symposium, ETS '04 (Ajaccio, May 2004), pp. 2-7. 2004. article at IEEExplore
A. Jutman. Shift register based TPG for at-speed interconnect BIST. In Proc. of 24th IEEE Int. Conf. on Microelectronics, MIEL '04 (Nis, May 2004), v. 2, pp. 751-754. 2004. article at IEEExplore
A. Jutman, E. Gramatova, T. Pikula, R. Ubar. E-learning tools for teaching self-test of digital electronics. In Proc. of 15th EAEEIE Ann. Conf. on Innovation in Education for Electrical and Information Engineering (Sofia, May 2004), pp. 267-272. 2004.
A. Jutman, A. Peder, J. Raik, M. Tombak, R. Ubar. Structurally synthesized binary decision diagrams. In Proc. of 6th Int. Wksh. on Boolean Problems (Freiberg, Sept. 2004), pp. 271-278. 2004.
A. Jutman, A. Sudnitson, R. Ubar, H.-D. Wuttke. Asynchronous e-learning resources for hardware design issues. In Proc. of Int. Conf. on Computer Systems and Technologies, CompSysTech 2004 (Ruse, June 2004), v. IV, pp. 11.1-11.6, 2004.
A. Jutman, A. Sudnitson, R. Ubar, H.-D. Wuttke. E-learning environment in the area of digital microelectronics. In Proc. of 5th IEEE Int. Conf. on Information Technology Based Higher Education and Training, ITHET 2004 (Istanbul, May/June 2004), pp. 278-283. IEEE, 2004. doi: 10.1109/ithet.2004.1358178
A. Jutman, R. Ubar, H.-D. Wuttke. Overview of e-learning environment for Web-based study of testing and diagnostics of digital systems. In Pre-Proc. of 5th European Wksh. on Microelectronics Education, EWME 2004 (Lausanne, Apr. 2004), pp. 173-176. 2004.
A. Jutman, R. Ubar, H.-D. Wuttke. Overview of e-learning environment for Web-based study of testing and diagnostics of digital systems. In A. M., Ionescu, M. Declercq, M. Kayal, Y. Leblebici, eds., Proc. of 5th European Wksh. on Microelectronics Education, EWME 2004 (Lausanne, Apr. 2004), pp. 253-258. Kluwer Acad. Publ., 2004.
N. Mazurova, J. Smahtina, R. Ubar. Hybrid functional BIST for digital systems. In Proc. of 9th Biennial Baltic Electronics Conf., BEC 2004 (Tallinn, Oct. 2004), pp. 205-208. TTU, 2004.
J. Raik, P. Ellervee, V. Tihhomirov, R. Ubar. Fast fault emulation for synchronous sequential circuits. In Proc. of 2nd East-West Design and Test Wksh., EWDTW 2004 (Alushta, Sept. 2004), pp. 35-40. 2004.
J. Raik, A. Krivenko, R. Ubar. Comparative analysis of sequential test generation approaches. In Proc. of 9th Biennial Baltic Electronics Conf., BEC 2004 (Tallinn, Oct. 2004), pp. 225-228. Tallinn Univ. of Techn., 2004.
J. Raik, E. Orasson, R. Ubar. Sequential circuits BIST with status BIT control. In Proc. of 11th Int. Conf. on Mixed Design of Integrated Circuits and Systems, MIXDES 2004 (Szczecin, June 2004), pp. 507-510. 2004.
J. Raik, R. Ubar. Enhancing hierarchical ATPG with a functional fault model for multiplexers. In Proc. of 7th IEEE Wksh. on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2004 (Stara Lesna, Apr. 2004), pp. 219-222. 2004.
J. Raik, R. Ubar. Targeting conditional operations in sequential test pattern generation. In Proc. of 9th IEEE European Test Symp., ETS 2004 (Ajaccio, May 2004), pp. 17-18. 2004.
J. Raik, V. Govind, R. Ubar. RT-level test point insertion for sequential circuits. In Proc. of 1st IEEE Int. Wksh. on Testability, IWoTA 2004 (Rennes, Nov. 2004), pp. 34-40. 2004. doi: 10.1109/iwota.2004.1428412
Y. A. Skobtsov, D. E. Ivanov, V. Y. Skobtsov, R. Ubar. Evolutionary approach to the functional test generation for digital circuits. In Proc. of 9th Biennial Baltic Electronics Conf., BEC 2004 (Tallinn, Oct. 2004), pp. 229-232. Tallinn Univ. of Techn., 2004.
A. Sudnitson. Register transfer low power design based on controller decomposition. In Proc. of 24th IEEE Int. Conf. on Microelectronics, MIEL 2004 (Nis, May 2004), v. 2, pp. 735-738. 2004. article at IEEExplore
R. Ubar. Diagnostic modelling of digital systems with decision diagrams. In Proc. of Tomsk State University, v. 1, n. 9, pp. 174-179, 2004.
R. Ubar, M. Aarna, M. Brik, J. Raik. High-level fault modeling in digital systems. In Proc. of Int. Conf. IWK (Ilmenau, Sept. 2004), pp. 486-491. 2004.
R. Ubar, M. Aarna, H. Kruus, J. Raik. How to generate high quality tests for digital systems. In Proc. of 2004 IEEE Int. Semiconductor Conf., CAS 2004 (Sinaia, Oct. 2004), v. 2, pp. 459-462. 2004. doi: 10.1109/smicnd.2004.1403048
R. Ubar, M. Jenihhin, G. Jervan, Z. Peng. An iterative approach to test time minimization for parallel hybrid BIST architecture. In Proc. of 5th IEEE Latin-American Test Wksh., LATW 2004, Digest of Papers (Cartagena, March 2004), pp. 98-103. 2004.
R. Ubar, M. Jenihhin, G. Jervan, Z. Peng. An iterative approach to test time minimization for parallel hybrid BIST architectures. In Proc. of System-on-Chip Conf. 2004 (Båstad, Apr. 2004). 2004.
R. Ubar, M. Jenihhin, G. Jervan, Z. Peng. Hybrid BIST optimization for core-based systems with test pattern broadcasting. In Proc. of 2nd IEEE Int. Wksh. on Electronic Design, Test and Applications, DELTA 2004 (Perth, Jan. 2004), pp. 3-8. IEEE, 2004. doi: 10.1109/delta.2004.10057
R. Ubar, N. Mazurova, J. Smahtina, E. Orasson, J. Raik. HyFBIST: hybrid functional built-in self-test in microprogrammed data-paths of digital systems. In Proc. of 11th Int. Conf. on Mixed Design of Integrated Circuits and Systems, MIXDES 2004 (Szczecin, June 2004), pp. 497-502. 2004.
R. Ubar, T. Vassiljeva, J. Raik, A. Jutman, M. Tombak, A. Peder. Optimization of structurally synthesized BDDs. In Proc. of 4th IASTED Int. Conf. on Modelling, Simulation and Optimization, MSO 2004 (Kauai, HW, Aug. 2004), pp. 234-240. Acta Press, 2004. article at publisher's website
R. Ubar, H.-D. Wuttke. Research and training scenarios for design and test of SOC. In Proc. of World Congress on Engineering and Technology Education (Guaruja/Santos, March 2004), pp. 320-324. 2004.
R. Ubar, H.-D. Wuttke. Research and training environment for digital design and test. In Proc. of 34th Ann. Frontiers in Education Conf., FIE 2004 (Savannah, GA, Oct. 2004), v. 3, pp. S3F/18-S3F/23. 2004. doi: 10.1109/fie.2004.1408779
V. Vislogubov, A. Jutman, H. Kruus, E. Orasson, J. Raik, R. Ubar. Diagnostic software with WEB interface for teaching purposes. In Proc. of 9th Biennial Baltic Electronics Conf., BEC 2004 (Tallinn, Oct. 2004), pp. 255-258. Tallinn Univ. of Techn., 2004.

Publikatsioone 2005:

M. Balas, M. Fisherova, E. Gramatova, A. Jutman, Z. Kotasek, O. Novak, T. Pikula, J. Raik, J. Strnadel, R. Ubar, J. Zahradka. Testing tools for training and education. In Proc. of 12th Int. Conf. Mixed Design of Integrated Circuits and Systems, MIXDES 2005 (Kraków, June 2005), pp. 671-676, 2005.
T. Bengtsson, A. Jutman, S. Kumar, R. Ubar. Delay testing of asynchronous NOC interconnects. In Proc. of 12th Int. Conf. Mixed Design of Integrated Circuits and Systems, MIXDES 2005 (Kraków, June 2005), pp. 419-424, 2005.
T. Bengtsson, A. Jutman, R. Ubar, S. Kumar. A method for crosstalk fault detection in on-chip buses. In Proc. of 23rd IEEE NORCHIP Conf., 2005 (Oulu, Nov. 2005), pp. 285-288. 2005. doi: 10.1109/norchp.2005.1597045
M. Brik, E. Fomina, R. Ubar. A proposal for optimisation of low-powered FSM testing. In Proc. of 3rd East-West Design & Test Wksh., EWDTW 2005 (Odessa, Sept. 2005), pp. 15-20, 2005.
S. Devadze, A. Sudnitson. FSM decomposition software for education and research. In Proc. of IEEE Int. Conf. Computer as a Tool, EUROCON 2005 (Belgrade, Nov. 2005), v. 1, pp. 839-482. IEEE, 2005. article at IEEExplore
E. Gramatová, R. Ubar, W.Pleskacz, M. Fischerová. Defects, faults, fault models. In O. Novák, E. Gramatová, R. Ubar, eds. Handbook of Testing Electronic Systems, ch. 2, pp. 26-96. Czech Techn. Univ. Publ. House, 2005.
E. Fomina, M. Brik, R. Vasilyev, A. Sudnitsyn. A new approach to state encoding of low power FSM. In Proc. of 3rd East-West Design & Test Wksh., EWDTW 2005 (Odessa, Sept. 2005), pp. 21-26, 2005.
E. Fomina, A. Sudnitson. Extended finite-state machine decomposition for low power. In Proc. of 19th Int. Conf. on Systems for Automation of Engineering and Research, SAER 2005 (Varna, Sept. 2005), pp. 126-131. 2005.
Z. He, G. Jervan, P. Eles, Z. Peng. Power-constrained hybrid BIST test scheduling in an abort-on-first-fail test environment. In Proc. of 8th Euromicro Conf. on Digital Systems Design, DSD 2005 (Porto, Aug./Sept. 2005), pp. 83-86. 2005. doi: 10.1109/dsd.2005.63
G. Jervan, R. Ubar, Z. Peng, P. Eles. An approach to system level design for testability. In M. Sonza Reorda, Z. Peng, M. Violante, eds., System-level Test and Validation of Hardware/Software Systems, v. 17 of Springer Series in Advanced Microelectronics, ch. 8, pp. 121-149. Springer, 2005. doi: 10.1007/1-84628-145-8_8
G. Jervan, R. Ubar, Z. Peng, P. Eles. Test generation: a hierarchical approach. In M. Sonza Reorda, Z. Peng, M. Violante, eds., System-level Test and Validation of Hardware/Software Systems, v. 17 of Springer Series in Advanced Microelectronics, ch. 5, pp. 67-81. Springer, 2005. doi: 10.1007/1-84628-145-8_5
G. Jervan, Z. Peng, R. Ubar, O. Korelina. An improved estimation technique for hybrid BIST test set generation. In Proc. of 8th IEEE Wksh. on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2005 (Sopron, Apr. 2005), pp. 182-185. 2005.
A. Jutman. Efficient at-speed interconnect BIST and diagnosis framework. In Informal Digest of Papers of 10th IEEE European Test Symp., ETS 2005 (Tallinn, May 2005), pp. 257-258. Tallinn Univ. of Techn., 2005.
A. Jutman. At-speed BIST for board-level interconnect. In Proc. of IEEE European Board Test Wksh., EBTW 2005 (Tallinn, May 2005). 2005.
A. Jutman, M. Kruus, A. Sudnitson, R. Ubar, H.-D. Wuttke. Web-based software package for e-learning and research training in digital system design. In Proc. of 32nd Int. Conf. on Information Technologies in Science, Education, Telecommunication, Business, IT+SE 2005 (Gurzuf, May? 2005), pp. 306-308. 2005.
A. Jutman, J. Raik, R. Ubar, V. Visloglubov. An educational environment for digital testing: hardware, tools, and Web-based runtime platform. In Proc. of 8th Euromicro Conf. on Digital Systems Design, DSD 2005 (Porto, Aug./Sept. 2005), pp. 412-419. 2005. doi: 10.1109/dsd.2005.15
A. Jutman, V. Rosin, A. Sudnitson, R. Ubar, H.-D. Wuttke. A system for teaching basic and advanced topics of IEEE 1149.1 boundary scan standard. In Proc. of 16th EAEEIE Ann. Conf. on Innovation in Education for Electrical and Information Engineering (Lappeenranta, June 2005). 2005.
A. Jutman, R. Ubar, J. Raik. Generic interconnect BIST for network-on-chip. In Proc. of 8th IEEE Wksh. on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2005 (Sopron, Apr. 2005), pp. 224-227. 2005.
A. Jutman, R. Ubar, J. Raik. New built-in self-test scheme for SoC interconnect. In Proc. of 9th World Multi-Conf. on Systemics, Cybernetics and Informatics, SCI 2005 (Orlando, FL, July 2005), v. 4, pp. 19-24. IIIS, 2005.
A. Jutman, R. Ubar, V. Rosin. A software system for IEEE 1149.1 boundary scan design, simulation and demonstration. In Proc. of IEEE European Board Test Wksh., EBTW 2005 (Tallinn, May 2005). 2005.
A. Yu. Matrosova, A. G. Pleshkov, R. R. Ubar. Construction of the tests of combinational circuit failures by analyzing the orthogonal disjunctive normal forms represented by the alternative graphs. Automation and Remote Control, v. 66, n. 2, pp. 313-327. 2005. doi: 10.1007/s10513-005-0054-9
A. Yu. Matrosova, A. G. Pleshkov, R. R. Ubar. Test generation for combinational circuits by orthogonal disjunctive normal forms and SSBDDs. Avtomatika i Telemekhanika, v. 2005, n. 2, pp. 158-174. 2005.
O. Novák, E. Gramatová, R. Ubar, eds. Handbook of Testing Electronic Systems. 402 pp. Czech Techn. Univ. Publ. House, 2005.
O. Novák, E. Gramatová, R. Ubar. IST project REASON - Handbook of testing electronic systems. In Proc. of 5th European Dependable Computing Conf., EDCC-5 (Budapest, Apr. 2005), pp. 15-18. IEEE, 2005.
J. Raik, P. Ellervee, V. Tihhomirov, R. Ubar. Improved fault emulation for synchronous sequential circuits. In Proc. of 8th Euromicro Conf. on Digital Systems Design, DSD 2005 (Porto, Aug./Sept. 2005), pp. 72-78. 2005. doi: 10.1109/dsd.2005.50
J. Raik, M. Jenihhin, R. Adelbert. Sequential circuits BIST synthesis from signal specifications. In Proc. of 23rd IEEE NORCHIP Conf. (Oulu, Nov. 2005), pp. 196-199. 2005. doi: 10.1109/norchp.2005.1597023
J. Raik, T. Nõmmeots, R. Ubar. A new testability calculation method to guide RTL test generation. J. of Electronic Testing: Theory and Applications, v. 21, n. 1, pp. 73-84. 2005. doi: 10.1007/s10836-005-5288-5
J. Raik, R. Ubar, S. Devadze, A. Jutman. Efficient single-pattern fault simulation on structurally synthesized BDDs. In M. dal Chin, M. Kaâniche, A. Pataricza, eds., Proc. of 5th European Dependable Computing Conf., EDCC-5 (Budapest, Apr. 2005), v. 3463 of Lect. Notes in Comput. Sci., pp. 332-344. Springer, 2005. doi: 10.1007/11408901_25
J. Raik, R. Ubar, J. Sudbrock, W. Kuzmicz, W. Pleskacz. Deterministic defect-oriented test generation for digital circuits. In Proc. of 6th IEEE Latin-American Test Wksh., LATW 2005 (Salvador de Bahia, March/Apr. 2005), pp. 325-330. 2005.
J. Raik, R. Ubar, J. Sudbrock, W. Kuzmicz, W. Pleskacz. DOT: new deterministic defect-oriented ATPG tool. In Proc. of 10th IEEE European Test Symp., ETS 2005 (Tallinn, May 2005), pp. 96-101. IEEE, 2005. doi: 10.1109/ets.2005.15
Y. A. Skobtsov, D. E. Ivanov, V. Y. Skobtsov, R. Ubar, J. Raik. Evolutionary approach to test generation for functional BIST. In Informal Digest of Papers of 10th IEEE European Test Symp., ETS 2005 (Tallinn, May 2005), pp. 151-155. Tallinn Univ. of Techn., 2005.
J. Sudbrock, J. Raik, R. Ubar, W. Kuzmicz, W. Pleskacz. Defect-oriented test- and layout-generation for standard-cell ASIC designs. In Proc. of 8th Euromicro Conf. on Digital Systems Design, DSD 2005 (Porto, Aug./Sept. 2005), pp. 79-82. 2005. doi: 10.1109/dsd.2005.30
R. Ubar. Decision diagrams and digital test (invited paper). In Proc. of 41th Int. Conf. on Microelectronics, Devices and Materials, MIDEM 2005 (Ribno at Bled, Sept. 2005), pp. 15-26. 2005.
R. Ubar. Digitaalsüsteemide diagnostika I: Diagnostiline modelleerimine. 148 lk. TTÜ Kirjastus, 2005.
R. Ubar. Introduction. In O. Novák, E. Gramatová, R. Ubar, eds. Handbook of Testing Electronic Systems, ch. 1, pp. 18-23. Czech Techn. Univ. Publ. House, 2005.
R. Ubar, E. Gramatová, M. Fischerová. Test generation techniques and algorithms. In O. Novák, E. Gramatová, R. Ubar, eds. Handbook of Testing Electronic Systems, ch. 3, pp. 99-173. Czech Techn. Univ. Publ. House, 2005.
R. Ubar, E. Orasson, J. Raik, H.-D. Wuttke. Teaching advanced test issues in digital electronics. In Proc. of 6th IEEE Int. Conf. on Information Technology Based Higher Education and Training, ITHET 2005 (Santo Domingo, July 2005), pp. S2B/1-S2B/6. 2005. doi: 10.1109/ithet.2005.1560318
R. Ubar, P. Prinetto, J. Raik. 10th IEEE European Test Symposium. IEEE Design & Test of Computers, v. 22, n. 5, pp. 480-481, 2005. doi: 10.1109/mdt.2005.106
R. Ubar, T. Shchenova, G. Jervan, Z. Peng. Energy minimization for hybrid BIST in a system-on-chip test environment. In Proc. of 10th IEEE European Test Symp., ETS 2005 (Tallinn, May 2005), pp. 2-7. IEEE, 2005. doi: 10.1109/ets.2005.16
R. Ubar, H.-D. Wuttke. Research and training environment for digital design and test. In Proc. of 8th IASTED Int. Conf. on Computers and Advanced Technology in Education, CATE 2005 (Oranjestadt, Aug. 2005), pp. 232-237. Acta Press, 2005. article at publisher's website
J. Öberg, J. Plosila, P. Ellervee. Automatic synthesis of asynchronous circuits from synchronous RTL descriptions. In Proc. of 23rd IEEE NORCHIP Conf., 2005 (Oulu, Nov. 2005), pp. 200-205. 2005. doi: 10.1109/norchp.2005.1597024

Publikatsioone 2006:

J. Aleksejev, A. Jutman, R. Ubar. LFSR polynomial and seed selection using genetic algorithm. In Proc. of 10th Baltic Electronics Conf., BEC 2006 (Laulasmaa, Oct. 2006), pp. 179-182. Tallinn Univ. of Techn., 2006. doi: 10.1109/bec.2006.311092
T. Bengtsson, A. Jutman, S. Kumar, R. Ubar, Z. Peng. Off-line testing of delay faults in NoC interconnects. In Proc. of 9th IEEE Euromicro Conf. on Digital Systems Design, DSD 2006 (Cavtat, Aug./Sept. 2006), pp. 677-680. IEEE, 2006. doi: 10.1109/dsd.2006.72
T. Bengtsson, A. Jutman, S. Kumar, R. Ubar. Analysis of a test method for delay faults in NoC interconnects. In Proc. of 4th East-West Design and Test Wksh., EWDTW '06 (Sochi, Sept. 2006), pp. 42-46. Kharkov Univ. of Techn., 2006.
T. Bengtsson, S. Kumar, A. Jutman, R. Ubar. Off-line testing of crosstalk induced glitch faults in NoC interconnects. In Proc. of 24th IEEE NORCHIP Conf., 2006 (Linköping, Nov. 2006), pp. 221-225. IEEE, 2006. doi: 10.1109/norchp.2006.329215
T. Borejko, A. Jutman, W. A. Pleskacz, R. Ubar. DefSim: measurement environment for CMOS defects. In Proc. of 25th Int. Conf. on Microelectronics, MIEL 2006 (Belgrade, May 2006), pp. 638-641. IEEE, 2006. article at IEEExplore
S. Devadze, J. Raik, A. Jutman, R. Ubar. Fault simulation with parallel critical path tracing for combinational circuits using structurally synthesized BDDs. In Proc. of IEEE Latin American Test Wksh., LATW 2006 (Buenos Aires, March 2006), pp. 97-102. IEEE, 2006.
L. Ehrenpreis, P. Ellervee, K. Tammemäe. Open source on-chip logic analyzer for FPGAs. In Proc. of 10th Baltic Electronics Conf., BEC 2006 (Laulasmaa, Oct. 2006), pp. 99-102. Tallinn Univ. of Techn., 2006. doi: 10.1109/bec.2006.311070
P. Ellervee, A. Arhipov, K. Tammemäe. Clock manipulation for heterogenous emulation environment. In Proc. of 24th IEEE NORCHIP Conf., 2006 (Linköping, Nov. 2006), pp. 213-216. IEEE, 2006. doi: 10.1109/10.1109/norchp.2006.329213
P. Ellervee, E. Ivask, M. Kruus. Improved VHDL input for high-level synthesis tool xTractor. In Proc. of 10th Baltic Electronics Conf., BEC 2006 (Laulasmaa, Oct. 2006), pp. 87-90. Tallinn Univ. of Techn., 2006. doi: 10.1109/bec.2006.311067
P. Ellervee, G. Jervan. How to emulate network-on-chip? In Proc. of 4th East-West Design and Test Wksh., EWDTW '06 (Sochi, Sept. 2006), pp. 282-286. Kharkov Univ. of Techn., 2006.
P. Ellervee, J. Raik, K. Tammemäe, R. Ubar. Environment for FPGA based fault emulation. Proc. of Estonian Acad. Sci.: Engineering, v. 12, n. 2-3, pp. 323-335, 2006.
P. Ellervee, U. Reinsalu, A. Arhipov. Teaching HDL for IT-students. In L.-R. Zheng, J. Nurmi, J. Liu, R.Weerasekera, H. Tenhunen, eds., Proc. of 6th Europ. Wksh. on Microelectronics Education, EWME 2006 (Stockholm, June 2006), pp. 112-115. KTH, 2006.
E. Fomina, A. Zakrevski. Graph embedding in Boolean hypercube. In Proc. of 10th Baltic Electronics Conf., BEC 2006 (Laulasmaa, Oct. 2006), pp. 131-134. Tallinn Univ. of Techn., 2006. doi: 10.1109/bec.2006.311078
V. Govind, J. Raik, R. Ubar. A generic synthesizable NoC switch with a scalable testbench. In Proc. of 10th Baltic Electronics Conf., BEC 2006 (Laulasmaa, Oct. 2006), pp. 91-94. Tallinn Univ. of Techn., 2006. doi: 10.1109/bec.2006.311068
V. Govind, J. Raik, R. Ubar. An external test approach for network-on-chip switches. In Proc. of 15th Asian Test Symp., ATS 2006 (Fukuoka, Nov. 2006), pp. 437-442. IEEE, 2006. doi: 10.1109/ats.2006.260967
V. Hahanov, M. Kaminska, E. Fomina. Testability analysis of digital design verification. In Proc. of 10th Baltic Electronics Conf., BEC 2006 (Laulasmaa, Oct. 2006), pp. 171-174. Tallinn Univ. of Techn., 2006. doi: 10.1109/bec.2006.311090
V. Hahanov, V. Obrizan, I. Hahanova, E. Fomina. Verification of digital system by a new asserting mechanism based on IEEE 1500 SECT standard. In Proc. of Int. Conf. on Mixed Design of Integrated Circuits and Systems, MIXDES 2006 (Gdynia, June 2006), pp. 544-548. IEEE, 2006. article at IEEExplore
K. Hermann, J. Raik, M. Jenihhin. TTBist: a DfT tool for enhancing functional test for SoC. In Proc. of 10th Baltic Electronics Conf., BEC 2006 (Laulasmaa, Oct. 2006), pp. 191-194. Tallinn Univ. of Techn., 2006. doi: 10.1109/bec.2006.311095
G. Jervan, A. Arhipov, P. Ellervee. FPGA based emulation environment. In Proc. of 2nd Int. Wksh. on Reconfigurable Communication.Centric Systems-on-Chip, ReCoSoc '06 (Montpellier, July 2006), pp. 146-151. Univ. Montpellier II, 2006.
G. Jervan, P. Eles, Z. Peng, R. Ubar, M. Jenihhin. Test time minimization for hybrid BIST of core-based systems. J. of Comput. Sci. and Techn., v. 21, n. 6, pp. 907-912, 2006. doi: 10.1007/s11390-006-0907-x
G. Jervan, Z. Peng, T. Shchenova, R. Ubar. A hybrid BIST energy minimization technique for system-on-chip testing. IEE Proc.: Computers and Digital Techniques, v. 153, n. 4, pp. 208-216, 2006. doi: 10.1049/ip-cdt:20050064
G. Jervan, T. Shchenova, R. Ubar. Hybrid BIST scheduling for NoC-based SoCs. In Proc. of 24th IEEE NORCHIP Conf., 2006 (Linköping, Nov. 2006), pp. 141-144. IEEE, 2006. doi: 10.1109/norchp.2006..329263
G. Jervan, R. Ubar, Z. Peng. Hybrid BIST methodology for testing core-based systems. Proc. of Estonian Acad. Sci.: Engineering, v. 12, n. 2-3, pp. 300-322, 2006.
A. Jutman, W. Pleskacz, N. Boiko, R. Ubar. DefSim-based exercises for studying defects in CMOS gates. In L.-R. Zheng, J. Nurmi, J. Liu, R. Weerasekera, H. Tenhunen, eds., Proc. of 6th Europ. Wksh. on Microelectronics Education, EWME 2006 (Stockholm, June 2006), pp. ?-?. Kungl. Tekn. Högskolan, 2006.
A. Jutman, A. Tsertov, R. Ubar. A tool for teaching pseudo-random TPG principles. In Proc. of 17th EAEEIE Conf. on Innovation in Education for Electrical and Information Engineering (Craiova, June 2006), pp. 182-187. Editura Universitaria Craiova, 2006.
A. Jutman, A. Tsertov, R. Ubar. A tool for advanced learning of LFSR-based testing principles. In Proc. of 10th Baltic Electronics Conf., BEC 2006 (Laulasmaa, Oct. 2006), pp. 175-178. Tallinn Univ. of Techn., 2006. doi: 10.1109/bec.2006.311091
A. Jutman, R. Ubar, V. Rosin, S. Devadze. Trainer 1149.1: a boundary-scan simulator. In Proc. of 5th IEEE Int. Board Test Wksh., BTW 2006 (Fort Collins, CO, Sept. 2006), ? pp. 2006.
M. Kruus, P. Ellervee. Four years of system-on-chip curricula: Experiences at Tallinn University of Technology. In L.-R. Zheng, J. Nurmi, J. Liu, R. Weerasekera, H. Tenhunen, eds., Proc. of 6th Europ. Wksh. on Microelectronics Education, EWME 2006 (Stockholm, June 2006), pp. 88-91. Kungl. Tekn. Högskolan, 2006.
W. Pleskacz, T. Borejko, A. Walkanis, V. Stopjakova, A. Jutman, Artur, R. Ubar. DefSim: CMOS defects on chip for research and education. In Proc. of 7th IEEE Latin-American Test Wksh., LATW 2006 (Buenos Aires, March 2006), pp. 74-79. IEEE, 2006.
W. Pleskacz, T. Borejko, A. Walkanis, V. Stopjakova, A. Jutman, Artur, R. Ubar. DefSim: CMOS defects on chip for research and education. In Informal Digest of Papers of 11th IEEE Europ. Test Symp., ETS 2006 (Southampton, May 2006), pp. 241-206. 2006
J. Raik, R. Ubar, T. Viilukas. High-level decision diagram based fault models for targeting FSMs. In Proc. of 9th IEEE Euromicro Conf. on Digital Systems Design, DSD 2006 (Cavtat, Aug./Sept. 2006), pp. 353-358. IEEE, 2006. doi: 10.1109/dsd.2006.60
T. Robal, M. Aarna, M. Brik. e-learning of digital logic: Using e-environments in teaching digital logic. In L.-R. Zheng, J. Nurmi, J. Liu, R. Weerasekera, H. Tenhunen, eds., Proc. of 6th Europ. Wksh. on Microelectronics Education, EWME 2006 (Stockholm, June 2006), pp. 120-123. Kungl. Tekn. Högskolan, 2006.
A. Smrikarov, S. Smrikarova, M. Kruus, A. Sudnitson. European thematic network for doctoral education in computing. In Proc. of 33rd Int. Conf. on Information Technologies in Science, Education, Telecommunication, Business, IT+SE 2006 (Gurzuf, May 2006), pp. 339-340. 2006.
A. Sudnitson, S. Devadze. Computer aided design support of FSM multiplicative decomposition. In Proc. of 4th East-West Design and Test Wksh., EWDTW '06 (Sochi, Sept. 2006), pp. 241-246. Kharkov Univ. of Techn., 2006.
A. Sudnitson, M. Kruus. E-learning tools for teaching the decomposition based digital synthesis. In L.-R. Zheng, J. Nurmi, J. Liu, R. Weerasekera, H. Tenhunen, eds., Proc. of 6th Europ. Wksh. on Microelectronics Education, EWME 2006 (Stockholm, June 2006), pp. 63-66. Kungl. Tekn. Högskolan, 2006.
R. Ubar, M. Brik, A. Jutman, J. Raik, T. Bengtsson, S. Kumar. Functional test generation for finite state machines. In Proc. of 10th Baltic Electronics Conf., BEC 2006 (Laulasmaa, Oct. 2006), pp. 205-208. Tallinn Univ. of Techn., 2006. doi: 10.1109/bec.2006.311099
R. Ubar, G. Jervan, H. Kruus, E. Orasson, I. Aleksejev. Optimization of the store-and-generate based built-in-self-test. In Proc. of 10th Baltic Electronics Conf., BEC 2006 (Laulasmaa, Oct. 2006), pp. 199-202. Tallinn Univ. of Techn., 2006. doi: 10.1109/bec.2006.311097
R. Ubar, A. Jutman, M. Kruus, H.-D. Wuttke. Applets for learning digital design and test. In Proc. of 1st Int. Conf. on Interactive Mobile and Computer Aided Learning, IMCL 2006 (Amman, Apr. 2006), pp. 1-6?. Univ. Kassel, 2006.
R. Ubar, M. Kruus. Success story of the Computer Engineering Department at the Tallinn University of Technology in EU projects. The Parliament Magazine: European Politics and Policy, n. 234, pp. 33, 2006.
R. Ubar, J. Raik, T. Evartson, M. Kruus, H. Lensen. Diagnostic modelling of digital systems with multi-level decision diagrams. In R. Wamkeue, ed., Proc. of 17th IASTED Int. Conf. on Modelling and Simulation, MS 2006 (Montréal, May 2006), pp. 207-212. Acta Press, 2006. article at publisher's website
R. Ubar, J. Raik, A. Jutman, P. Ellervee. Digital electronics design and test at Computer Engineering Department of Tallinn University of Technology. The House Magazine: The Parlamentary Weekly, v. 32, n. 1198, p. 42, 2006.
H.-D. Wuttke, A. Sudnitson, K. Henke. E-learning tools for teaching the design and validation of finite state machines. In E-Learning and the Knowledge Society, pp. 327-341. Communication and Cognition, Gent, 2006.

Publikatsioone 2007:

P. Ellervee, A. Arhipov, U. Reinsalu. Using emulation for system model analysis. In Wksh. Digest of DATE 2007 Wksh. on Diagnostic Services in Network-on-Chips: Test, Debug and On-Line Monitoring (Nice, Apr. 2007), pp. 280-282. 2007.
P. Ellervee, J. Raik, R. Ubar, K. Tammemäe. FPGA-based fault emulation of synchronous sequential circuits. IET Computers and Digital Techniques, v. 1, n. 2, pp. 70-76, 2007. doi: 10.1049/iet-cdt:20050065
P. Ellervee, U. Reinsalu, A. Arhipov. Translating behavioral VHDL for emulation. In Proc. of 25th IEEE NorChip Conf. 2007 (Aalborg, Nov. 2007), pp. ?-?. IEEE, 2007.
G. Guglielmo, F. Fummi, M. Jenihhin, G. Pravadelli, J. Raik, R. Ubar. On the combined use of HLDDs and EFSMs for functional ATPG. In Proc. of 5th IEEE East-West Design and Test Symp., EWDTS 2007 (Yerevan, Sept. 2007), pp. 503-509. IEEE, 2007.
M. Jenihhin, J. Raik, A. Chepurov, R. Ubar. Assertion checking with PSL and high-level decision diagrams. In Proc. of 8th IEEE Wksh. on RTL and High Level Testing, WRTLT '07 (Beijing, Oct. 2007), pp. ?-?. IEEE, 2007.
M. Jenihhin, J. Raik, R. Ubar, W. A. Pleskacz, M. Rakowski. Layout to logic defect analysis for hierarchical test generation. In Proc. of 10th IEEE Wksh. on Design and Diagnostics of Electronic Circuits and Systems, DDECS '07 (Kraków, Apr. 2007), pp. 35-40. IEEE, 2007. doi: 10.1109/ddecs.2007.4295251
G. Jervan, H. Kruus, E. Orasson, R. Ubar. Hybrid BIST optimization using reseeding and test set compaction. In Proc. of 10th Euromicro Conf. on Digital System Design, DSD 2007 (Lübeck, Aug. 2007), pp. 596-603. IEEE, 2007. doi: 10.1109/dsd.2007.4341529
G. Jervan, H. Kruus, E. Orasson, R. Ubar. Optimization of memory-constrained hybrid BIST for testing core-based systems. In Proc. of 2007 Int. Symp. on Industrial Embedded Systems, SIES '07 (Costa da Caparica, July 2007), pp. 71-77. IEEE, 2007. doi: 10.1109/sies.2007.4297319
G. Jervan, M. Kruus, E. Rüstern. Graduate school in information and communication technologies: experiences at Tallinn University of Technology. In Proc. of 2007 IEEE Int. Conf. on Microelectronic Systems Education, MSE '07 (San Diego, CA, June 2007), pp. 25-26. IEEE, 2007. doi: 10.1109/mse.2007.47
A. Jutman, A. Tsertov, A. Tsepurov, I. Aleksejev, R. Ubar, H.-D. Wuttke. BIST analyzer: a training platform for SoC testing. In Proc. of 37th ASEE/IEEE Frontiers in Education Conf., FIE '07 (Milwaukee, Oct. 2007), pp. SH3-8-SH3-13. IEEE, 2007. doi: 10.1109/fie.2007.4418125
A. Mellik, J. Raik. Comparative mixed-signal test method and toolset. In Proc. of IEEE Int. Wksh. on Open Source Test Technology Tools, IOST3 2007 (Berkeley, CA, May 2007), ? pp. 2007.
J. Raik, V. Govind, R. Ubar. An external diagnosis method for network-on-a-chip. In Wksh. Digest of DATE 2007 Wksh. on Diagnostic Services in Network-on-Chips: Test, Debug and On-Line Monitoring (Nice, Apr. 2007), pp. ?-?. 2007.
J. Raik, R. Ubar, V. Govind. Test configurations for diagnosing faulty links in NoC switches. In Proc. of 12th IEEE European Test Symp., ETS '07 (Freiburg, May 2007), pp. 29-34. IEEE, 2007. doi: 10.1109/ets.2007.41
J. Raik, R. Ubar, M. Jenihhin, A. Chepurov. PSL assertion checking with temporally extended high-level decision diagrams. In Proc. of 9th IEEE Latin-American Test Wksh. (Puebla, Feb. 2008), IEEE, to appear.
J. Raik, R. Ubar, A. Jutman, I. Aleksejev. A scalable test set compaction method for sequential circuits. In Proc. of 9th IEEE Latin-American Test Wksh. (Puebla, Feb. 2008), IEEE, to appear.
J. Raik, R. Ubar, A. Krivenko, M. Kruus. Hierarchical identification of untestable faults in sequential circuits. In Proc. of 10th Euromicro Conf. on Digital System Design, DSD 2007 (Lübeck, Aug. 2007), pp. 668-671. IEEE, 2007. doi: 10.1109/dsd.2007.4341539
J. Raik, R. Ubar, T. Viilukas, M. Jenihhin. Mixed hierarchical-functional fault models for targeting sequential cores. J. of Systems Architecture, to appear.
U. Reinsalu, A. Arhipov, T. Evartson, P. Ellervee. HDLs for students with different background. In Proc. of 2007 IEEE Int. Conf. on Microelectronic Systems Education, MSE '07 (San Diego, CA, June 2007), pp. 69-70. IEEE, 2007. doi: 10.1109/mse.2007.49
A. Sudnitson, S. Devadze. Web-based computer aided design support of finite state machine additive decomposition for low power. In Proc. of 5th IEEE East-West Design and Test Symp., EWDTS 2007 (Yerevan, Sept. 2007), pp. 494-498. IEEE, 2007.
M. Tagel, G. Jervan. Deterministic traffic generator for NoC simulator. In Wksh. Digest of DATE 2007 Wksh. on Diagnostic Services in Network-on-Chips: Test, Debug and On-Line Monitoring (Nice, Apr. 2007), pp. 288-290. 2007.
R. Ubar, S. Devadze, M. Jenihhin, J. Raik, G. Jervan, P. Ellervee. Hierarchical calculation of malicious faults for evaluating the fault-tolerance. In Proc. of 4th IEEE Int. Symp. on Electronic Design, Test and Applications, DELTA '08 (Hongkong, Jan. 2008), IEEE, to appear.
R. Ubar, S. Devadze, J. Raik, A. Jutman. Ultra fast parallel fault analysis on structurally synthesized BDDs. In Proc. of 12th IEEE European Test Symp., ETS '07 (Freiburg, May 2007), pp. 131-136. IEEE, 2007. doi: 10.1109/ets.2007.43
R. Ubar, S. Devadze, J. Raik, A. Jutman. Parallel fault backtracing for calculation of fault coverage. In Proc. of Int. Conf. on Microelectronics, Devices and Materials and Wksh. on Electronic Testing, MIDEM '07 (Bled, Sept. 2007), pp. 165-170. MIDEM, 2007.
R. Ubar, S. Devadze, J. Raik, A. Jutman. Parallel Fault Backtracing for Calculation of Fault Coverage. In Proc. of 13th Asia and South Pacific Design Automation Conf., ASP-DAC 2008 (Seoul, Jan. 2008), IEEE, to appear.
R. Ubar, T. Evartson, H. Lensen, M. Aarna. Hierarchical fault diagnosis in embedded digital systems with multi-level decision diagrams. In Proc. of 5th Int. Conf. on Industrial Automation (Montréal, July 2007), pp. 1-6. 2007.
R. Ubar, G. Jervan, J. Raik, M. Jenihhin, P. Ellervee. Dependability evaluation in fault-tolerant systems with high-level decision diagrams. In Proc. of 52nd Int. Scientific Coll., IWK 2007 (Ilmenau, Sept. 2007), v. 2, pp. 147-152. Universitätsverlag Ilmenau, 2007.
R. Ubar, A. Jutman, S. Devadze, H.-D. Wuttke. Bringing research issues into lab scenarios on the example of SoC testing. In Proc. of 2007 Int. Conf. on Engineering Education, ICEE 2007 (Coimbra, Sept. 2007), pp. ?-?. 2007.
R. Ubar, A. Jutman, M. Kruus, E. Orasson, S. Devadze, H.-D. Wuttke. Learning digital test and diagnostics via Internet. Int. J. of Online Engineering, v. 3, n. 1, 2007, 9 pp., 2007. article at journal's website
R. Ubar, S. Kostin, J. Raik. Built-in self diagnosis with multiple signature analyzers in digital systems. In Proc. of 9th IEEE Latin-American Test Wksh., LATW 2008 (Puebla, Feb. 2008), IEEE, to appear.
R. Ubar, S. Kostin, J. Raik. Embedded diagnosis in digital systems. In Proc. of 26th Int. Conf. on Microelectronics, MIEL 2008 (Nis, May 2008), IEEE, to appear.
R. Ubar, S. Kostin, J. Raik, T. Evartson, H. Lensen. Fault diagnosis in intergrated circuits with BIST. In Proc. of 10th Euromicro Conf. on Digital System Design, DSD 2007 (Lübeck, Aug. 2007), pp. 604-610. IEEE, 2007. doi: 10.1109/dsd.2007.4341530
R. Ubar, S. Kostin, J. Raik, M. Kruus. Experimental comparison of different diagnosis algorithms in the BIST environment. In F. de Felice, ed., Proc. of 16th IASTED Int. Conf. on Applied Simulation and Modelling, ASM 2007 (Palma de Mallorca, Aug. 2007), pp. 88-92. Acta Press, 2007. article at publisher's website
R. Ubar, J. Raik, H. Kruus, H. Lensen, T. Evartson. Diagnostic modelling of digital systems with binary and high-level decision diagrams. In L. L. Bonilla, M. Moscoso, G. Platero, J. M. Vega, eds., Progress in Industrial Mathematics at 14th Europ. Conf. for Mathematics in Industry, ECMI 2006 (Madrid, July 2006), v. 12 of Mathematics in Industry, pp. 902-907. Springer, 2008. doi: 10.1007/978-3-540-71992-2_158
H.-D. Wuttke, R. Ubar, K. Henke, A. Jutman. Assessment of student's design results in e-learning-scenarios. In Proc. of 8th Int. Conf. on Information Technology Based Higher Education and Training, ITHET 2007 (Kumamoto, July 2007), pp. 1-6. IEEE, 2007.

Doktorikaitsmised 2002:

M. Brik, Investigation and development of test generation methods for control part of digital systems, TTÜ, juhendaja R. Ubar, oponendid M. Šeinauskas (Kaunase Tehnikaülikool), V. Hahhanov (Harkovi Rahvuslik Raadioelektroonika Ülikool), 10.10.2002

Doktorikaitsmised 2004:

A. Jutman, Selected issues of modeling, verification and testing of digital systems, TTÜ, juhendaja R. Ubar, oponendid M. Renovell (Univ. Montpellier 2), M. Glesner (Techn. Univ. Darmstadt), 6.10.2004

Doktorikaitsmised 2005:

G. Jervan, Hybrid built-in self-test and test generation techniques for digital systems, Linköpings Univ., juhendaja Z. Peng, oponent J. P. Teixeira (Inst. Superior Técnico, Lissabon), 20.5.2005
J. Fomina, Low power finite state machine synthesis, TTÜ, juhendaja A. Sudnitsõn, oponendid V. Hahhanov (Harkovi Rahvuslik Raadioelektroonika Ülikool), A. Zakrevski (Informaatikaprobleemide Ühendinstituut, Minsk), 15.12.2005. thesis at TUT DL

Doktorikaitsmised 2006:

E. Ivask, Digital test in web-based environment, TTÜ, juhendaja R. Ubar, oponendid H. Krupnova (STMicroelectronics, Grenoble), G. Elst (Fraunhofer Institute for Integrated Circuits, Dresden), 5.7.2006. thesis at TUT DL

Doktorikaitsmised 2007:

E. Orasson, Hybrid built-in self-test: methods and tools for analysis and optimization of BIST, TTÜ, juhendaja R. Ubar, oponendid E. Aas (Norges Teknisk-Naturvitenskapelige Universitet, Trondheim), B. Straube (Fraunhofer Institute for Integrated Circuits, Dresden), 24.10.2007. thesis at TUT DL

Viimane uuendus 30.1.2008